1. Field of the Invention
The present invention relates to a memory circuit having non-volatile memory such as flash memory, and more particularly to a memory circuit which can optimize the level of boosted voltage when driving wordlines at the boosted voltage to which a power source voltage is boosted by a prescribed ratio.
2. Description of the Related Art
Memory devices such as EEPROM or flash memory, which is a type of non-volatile memory, use MOS transistors having floating gates as the memory cells. Writing (programming) by adding electrons to the floating gate results in a storage state of data 0; erasing by pulling electrons from the floating gates results in a storage state of data 1. The control gates connected to the wordlines are driven at prescribed high voltages and the different threshold values of the memory cell transistors, which differ according to the storage states, are read by the presence or non-presence of electric current.
With recent requirements for reducing voltage, lower power source voltages of 2.7-3.6 V, for example, are the trend. On the other hand, the MOS transistors with floating gates which constitute memory cells require that wordlines be driven at higher voltages of 5.5 V, for example, in order to detect different threshold values during reading. Consequently, a boosted voltage generating circuit is provided internally; the boosted voltage generating circuit raises the power source voltage Vcc and generates a boosted voltage VPW which is at the wordline driving level during reading. The operation of boosting the power source voltage Vcc to a prescribed ratio is carried out by this boosted voltage generating circuit.
However, the wordline voltage during reading has upper and lower limits for the following reasons. The control gates of a plurality of memory cell transistors are connected to the wordlines. Consequently, the wordlines are driven as high as the boosted voltage for the memory cells selected for reading, and if the boosted voltage is too high, excess voltage is applied between the drains and control gates of the selected memory cell transistors; this may bring about the injection of electrons to the floating gate thereof and result in a slight writing operation. Consequently, the upper limit of the boosted voltage is set somewhat below the voltage at which the operation of writing to such a selected memory cell transistor is limited to some extent.
Meanwhile, the lower limit of the boosted voltage is set at a level which guarantees the reading of the programmed memory cell transistor. The erase operation of a transistor with a floating gate pulls electrons from the floating gate and causes the threshold voltage thereof to drop. Because of dispersion within the prescribed block, which is the unit erased, an excessive number of electrons is pulled from some of the memory cell transistors and the threshold voltages thereof become negative. As a result, even if the wordlines are maintained at ground, some leakage current will flow into such transistors. Consequently, in the case of the selection of memory cell transistors in the program state (data 0) on the same bitlines as this type of over-erased memory cell transistor, current should not flow to those bitlines in a proper operation, but leakage current from the aforementioned over-erased transistors is generated.
Meanwhile, a reference memory cell transistor for reading is provided for the read operation. The boosted voltage is applied to this reference memory cell transistor and the flowing current is used as the reference current for reading. Consequently, this reference current is set so as to be greater than the bitline current (allowable leakage current) when a program state cell transistor is selected and smaller than the bitline current when an erase state cell transistor is selected.
Consequently, normal reading of the program state memory cell transistor becomes impossible when the boosted voltage is reduced and the reference current of the reference memory cell transistor becomes less than the allowed leakage current value. This is the lower limit for the boosted voltage.
In addition to the recent demands for lowering power source voltage, the ability to comply to a broader range of power source voltages is required. For such power source voltages, the level of the internally produced boosted voltage must be between the aforementioned upper and lower limit values.